How to accelerate innovation in IC technology with chiplets and 3D ICs: Full podcast

0:03 From the drive towards monetization to the integration of complex functions through advanced packaging and 3D ICs, the future of IC technology is being reshaped before our very eyes. And with the industry projected to reach a staggering $ 1 trillion market by 2030, companies are faced with the challenge of accelerating innovation while managing the ever-increasing complexities, the 3D IC design and manufacturing. With that, let me welcome you to the 2025 Siemens EDA podcast series on 3D IC chiplet ecosystems, brought to you by the Siemens thought leadership team. I'm your host, John McMillan. This podcast series dives into the exciting world of semiconductor chiplet integration and advanced

0:50 technology platforms using two and a half and 3D techniques. I talk to industry leaders and subject matter experts to discuss the latest 3D IC industry trends and roadmaps, and uncover how the semiconductor industry is working diligently to make 3D IC mainstream. In today's podcast, I'm excited to be joined by my special guest, Jan Vardaman, President of TechSearch International, to discuss the advanced packaging and heterogeneous integration roadmap for semiconductor scaling. Welcome Jan, and thank you for taking the time to talk with me today. And before we dive into today's discussion, please tell our listeners a little about yourself and your current role and background. Our company's 37 years old, and we've been covering the developments in packaging since before it became so popular. And our focus

1:39 is totally on advanced packaging and the developments that we're seeing. And the pace, I must say, is faster than ever. And so we are very excited to be discussing some of these topics with everyone. So as a company that is laser focused on the semiconductor packaging market, what do you see as the main drivers for advanced integration, heterogeneous or homogeneous silicon from a technology and business point of view? Well, always cost is a major driver. So the reason that we're seeing so much interest in the idea of the chiplet is it's a new way to design an IC. And we can really no longer afford to fabricate everything as a monolithic die on the most

2:26 expensive nodes. Now that being said, it doesn't mean that we can't do... We won't still continue with monolithic die because if you can, you should do that. But there are many cases where part of the IC design really doesn't scale as well as the logic does. So why would you want to fabricate a large portion of that die in a very expensive leading edge node, like a five, three nanometer node when it really could be fabricated in a legacy node so that you could save money on your silicon fab cost? So it's really all about silicon fab cost and the idea of disaggregating the design,

3:11 the IC design. And then putting it back together in the package and using that package in your system to achieve the basically highest performance that you can possibly get. And in many cases, you can also achieve a more energy efficient solution in terms of your picajoules per bit measurement. Got you. Wow, that's really insightful. So given this, is there any specific market segments and industries that are driving these activities? For example, we hear a lot about hyperscale AI, HPC, high performance compute, but is that it or is there a broader picture and a broader set of players and or markets involved? Well, there are other

3:58 applications. Obviously today, our Nvidia processors, up until Blackwell have really been a monolithic die design that has been in a package with HBM, which I would consider classifying that as a heterogeneous integration where you have the communication between the GPU and the HBM. In the case of the chiplet designs that have been implemented, you've seen many designs over the last several years implemented by AMD for servers, desktops, gaming, many different applications. And the arguments that they have made that the savings on the silicon side makes up for any additional cost for a package. And it's

4:44 tremendous, really tremendous savings on the silicon side. But they have the ability to do this architecture inside internally with the capabilities that they have. What a lot of people want to see is the ability to include third-party chiplet designs into their design. And so the industry's working on that, but that has a lot of challenges including test and the communication between the chiplet's protocols and standardization of those protocols. So it's going to be interesting to see how things develop over time, but certainly we're in an era where we're moving in that direction. Now, the new GPU for AI from Nvidia is basically using what is considered or called the chiplet architecture in a new package

5:32 from TSMC called CoWoS-L, which is an RDL interposer. The AMD MI300 series that is in production today is a chiplet design. And interestingly enough that Chiplet design uses a 3D stacking, a hybrid bonding, and they are able to achieve some really good energy efficiency in that design, and certainly their performance is outstanding. So you've seen an introduction of something that is both a heterogeneous integration solution as well as a chiplet design, and I think that you'll see more of that moving forward. So each company has a different approach depending upon their internal capabilities, their design,

6:18 philosophy, their tools. So you'll see a variety of different options offered. Yeah, got you. So clearly there's a much broader set of industry interest than what we typically hear about. Now, some of these industry and markets are different. Are they all looking for the same integration solution or platform, or do they have different needs that may require a different technology or platform? And if so- Well, I think you're referring to the packages. And the packages... Everybody has a different approach depending upon their particular supply chain, their capabilities. And so for example, you see that the MI300 series is on a silicon interposer, a CoWoS done by turnkey by TSMC. You see that the new Black...

7:07 And the Hopper series had been on also the Silicon interposer, the CoWoS. The new Blackwell uses the CoWoS-L as I mentioned, with an RDL interposer as opposed to a silicon interposer. If you look at some of the other solutions out there, you'll see the Amazon using a CoWoS-R, which is the RDL solution without Bridges, the CoWoS-L solution having silicon bridges. If you look at some of the things that Intel has introduced, that they favor the technology of the embedded bridge in the laminate substrate. And so that's the technology, that solution that they have offered for some of their server products and some of their high-end applications. So you see a variety of options, of package

7:53 options. So a chiplet is really the architecture and how you design the IC. And then it goes into the package that you choose based on your philosophy of design and a package design and your supply chain. Got you. Yeah, it makes it a lot clearer for me, and I hope for our listeners as well. Now, there's been a lot published recently about substrate materials, silicon, RDL, glass core, flexible glass, organic interposer, bridges, et cetera. Are these all competing against each other or do they have specific applications? And if so, where and how should the design team choose one over the other? Well, I mean, it all depends on what you're trying to do and achieve.

8:38 And like I said, your supply chain. For example, if you use a silicon interposer or you use an RDL interposer, you still have a buildup substrate that it's connected to typically with a C4 bump. And so you have your die and your interposer and then your substrate. And that RDL structure can either have an embedded silicon bridge or not. If you're doing something... And those solutions have been favored by AMD and Nvidia in the highest performance cases. If you are Intel, they have favored the idea of the EMIB solution where the bridge is embedded in a laminate substrate so that your highest density is achieved

9:24 where the bridge is located. So the idea being if you don't need a high density across the space, and so there is not an additional substrate. Now there's been a lot of debate as to which solution is the most cost-effective. And again, that depends on your design and a lot of other factors including your supplier chain and a number of things. So the jury is still out, and I think it's very designed dependent. So those are the options. We do see a lot more people moving in the direction of RDL interposers, possibly because we believe that that allows the pitch scaling to a much higher density than you would get with using a laminate organic

10:09 type substrate even with the Silicon Bridge. But there's some new developments with using a Silicon Bridge, maybe with TSVs or some other capabilities that might allow some finer pitch scaling. But it's all about looking at it from your perspective of what your capabilities are internally and then what is the system level performance that you're trying to achieve and how can you best achieve that. And basically, the bottom line at the end of the day is there's no one single packaging solution that we can point to and say, this is it, because it's going to depend on a lot of different factors. Thank you, Jan. This has been very informative and thank you for joining me today and for sharing your knowledge and thoughts on this exciting and fast moving area of technology. I'd also like

10:57 to take a moment to mention that the Siemens Innovator 3D IC platform was named the winner of the esteemed 3D InCites 2025 Award for Technology Enablement. If you're not familiar with the Innovator 3D IC platform, it is an AI enhanced co-design tool that ensures digital continuity through system centric planning for die interposer package and PCV design by providing early insights into thermal, mechanical and electrical performance, reducing design iterations and accelerating development. That award was quite an honor. I hope you found today's podcast educational and insightful. I certainly did and I feel a lot more empowered now when I talk about advanced semiconductor packaging with designers. Then we're all out of time for now. But thank you for joining us. But be sure to check the show notes to learn more about 3D IC and the

11:43 Innovator 3D IC platform, and be sure to subscribe so you don't miss the next episode of the 3D IC Podcast.